1. Field of the Invention
The present invention relates generally to timer circuits and, in particular, to timer circuits having programmable decode circuitry capable of providing adjustable duration timing pulses.
2. Background Art
In many integrated circuits, there is a requirement that certain functions be carried for a relatively precise time period. By way of example, in flash memory systems, the memory cells are programmed and erased by application of certain voltages to the flash memory cells for a fixed duration of time. A typical programming pulse may have a duration on the order of one microsecond. A typical erase pulse may have a duration on the order of one to a hundred milliseconds.
In addition, the characteristics of flash memory cells may vary from memory to memory, even for memories having a common design. Much of these variations are due to processing variations and other well known factors which affect the characteristics a memory and which are not readily controllable. Because of these variations in memory characteristics, the voltage pulses used in carrying out the memory functions such as programming are set to a value which will take into account such variations in characteristics. However, the pulse durations are not optimized to take into account the particular characteristics of a given memory. Thus, memory performance is reduced.
The present invention pertains to a timer circuit which, while capable of providing a wide range of pulse durations ranging from the microsecond range to the millisecond range, also provides the capability of generating a large number of different pulses, each having a duration which can be precisely adjusted. This latter feature permits, for example, the pulse widths to be selected after fabrication so that the characteristics of the memory may be taken into account. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
A timer circuit is disclosed which includes a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is adjustable. A frequency divider is included, typically implemented in the form of a counter circuit, having a plurality of stages, with each stage dividing the input by two. The frequency divider is responsive to the periodic timing signal for providing a plurality of frequency divided outputs.
The timer circuit is further provided with decode circuit means for combining selected ones of the frequency divided outputs based upon decode parameters and generating a timer circuit output pulse having a duration determined by the selected ones of the frequency divided outputs. Typically, the decode circuit means includes a multiplexer which receives the frequency divided outputs, either directly or in combination form, and outputs one of the received signals in response to the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the output pulse duration will be retained after power to the timer circuit has been interrupted.